High speed latch comparators

Details High speed latch comparators High speed latch comparators

2002-02-27

2003-10-28

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S211000

Reexamination Certificate

active

06639430

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high speed latch comparators.
2. Background Art
Commercialization of the Internet has proven to be a mainspring for incentives to improve network technologies. Development programs have pursued various approaches including strategies to leverage use of the existing Public Switched Telephone Network and plans to expand use of wireless technologies for networking applications. Both of these approaches (and others) entail the conversion of data between analog and digital formats. Therefore, it is expected that analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) will continue to perform critical functions in many network applications.
Because ADCs find uses in a wide variety of applications, design of these circuits has evolved along many paths to yield several distinct architectures, including “delta sigma,” “successive approximation,” “pipelined,” and “flash.” Each architecture has its benefits and drawbacks. Paramount among these is a tradeoff between bandwidth and degree of resolution.
FIG. 1
is a graph
100
that shows the tradeoff between bandwidth and degree of resolution for the various ADC architectures. Graph
100
comprises a “degree of resolution” axis
102
and a “bandwidth” axis
104
. The relative positions of the different ADC architectures are plotted with respect to axes
102
,
104
: a “delta sigma” region
106
, a “successive approximation” region
108
, a “pipelined” region
110
, and a “flash” region
112
. In the design of network technologies, data conversion has often presented itself as a bottleneck that impedes the rate at which information is transmitted. Therefore, those ADC architectures that can support large bandwidths for rapid transfers of data have been favored for network applications.
FIG. 2A
is a block diagram of an exemplary conventional two-bit flash ADC
200
. ADC
200
comprises a first comparator “A”
202
, a second comparator “B”
204
, a third comparator “C”
206
, a priority encoder
208
, a first resistor “R
1
”
210
, a second resistor “R
2
”
212
, a third resistor “R
3
”
214
, and a fourth resistor “R
4
”
216
. Each of R
1
210
, R
2
212
, R
3
214
, and R
4
216
has the same measure of resistance. R
1
210
, R
2
212
, R
3
214
, and R
4
216
are connected in series between an analog ground “V
AG
”
218
and a supply voltage “V”
220
. R
1
210
is connected between V
AG
218
and a first node “N
1
”
222
. R
2
212
is connected between N
1
222
and a second node “N
2
”
224
. R
3
214
is connected between N
2
224
and a third node “N
3
”
226
. R
4
216
is connected between N
3
226
and V
220
. In this configuration, the voltage at N
1
222
is equal to V/4, the voltage at N
2
224
is equal to V/2, and the voltage at N
3
226
is equal to 3V/4.
The inverting terminals of comparators A
202
, B
204
, and C
206
are connected to, respectively, N
1
222
, N
2
224
, and N
3
226
. An analog signal “x”
228
is received at an input
230
, which is connected to the noninverting terminals of comparators A
202
, B
204
, and C
206
. A quantized signal is produced at the output terminal of each comparator. Quantized signals “w
1
”
232
, “w
2
”
234
, and “w
3
”
236
are produced at the output terminals of, respectively, comparators A
202
, B
204
, and C
206
. Each quantized signal has a voltage with a value “LOW” or a value “HIGH” depending upon whether a corresponding value of the voltage of analog signal x
228
is less than (or equal to) or greater than the voltage at the inverting terminal of the corresponding comparator (i.e., the reference voltage of the comparator). For example, when the value of the voltage of analog signal x
228
is less than or equal to V/4, the values of the voltages of w
3
236
, w
2
234
, and w
1
232
are equal to, respectively, LOW, LOW, and LOW. When the value of the voltage of analog signal x
228
is less than or equal to V/2, but greater than V/4, the values of the voltages of w
3
236
, w
2
234
, and w
1
232
are equal to, respectively, LOW, LOW, and HIGH. When the value of the voltage of analog signal x
228
is less than or equal to 3V/4, but greater than V/2, the values of the voltages of w
3
236
, w
2
234
, and w
1
232
are equal to, respectively, LOW, HIGH, and HIGH. When the value of the voltage of analog signal x
228
is less than or equal to V, but greater than 3V/4, the values of the voltages of w
3
236
, w
2
234
, and w
1
232
are equal to, respectively, HIGH, HIGH, and HIGH. It is because quantized signals w
1
232
, w
2
234
, and w
3
236
are produced simultaneously that two-bit flash ADC
200
, also referred to as a “parallel-comparator” ADC, is capable of supporting large bandwidths for rapid transfers of data.
The output terminals of comparators A
202
, B
204
, and C
206
are connected to priority encoder
208
. Quantized signals w
1
232
, w
2
234
, and w
3
236
are received by priority encoder
208
, which processes them to produce, at an output
238
, a two-bit digital signal “y” comprising a least significant bit (LSB) signal “y
1
”
240
and a most significant bit (MSB) signal “y
2
”
242
.
FIG. 2B
is a truth table
244
for priority encoder
208
. In truth table
244
, LOW and HIGH are encoded as, respectively, 0 and 1. When quantized signals w
3
236
, w
2
234
, and w
1
232
are equal to, respectively, 0, 0, and 0, bit signals y
2
242
and y
1
240
are equal to, respectively, 0 and 0, which corresponds to binary number 0. When quantized signals w
3
236
, w
2
234
, and w
1
232
are equal to, respectively, 0, 0, and 1, bit signals y
2
242
and y
1
240
are equal to, respectively, 0 and 1, which corresponds to binary number 1. When quantized signals w
3
236
, w
2
234
, and w
1
232
are equal to, respectively, 0, 1, and 1, bit signals y
2
242
and y
1
240
are equal to, respectively, 1 and 0, which corresponds to binary number 2. When quantized signals w
3
236
, w
2
234
, and w
1
232
are equal to, respectively, 1, 1, and 1, bit signals y
2
242
and y
1
240
are equal to, respectively, 1 and 1, which corresponds to binary number 3.
The skilled artisan will appreciate that, with additional comparators and resistors and by using a priority encoder capable of processing additional quantized signals, flash ADC
200
can be modified so that digital signal y comprises more than two bit signals. Alternatively, flash ADC
200
can be modified so that digital signal y comprises one bit signal.
Implementations of comparators A
202
, B
204
, and C
206
often use latch circuits, and are referred to as latch comparators.
FIG. 3
is a schematic diagram of an exemplary conventional latch circuit
300
that can be used in an implementation of any of comparators A
202
, B
204
, or C
206
. Latch circuit
300
comprises a bistable pair
302
connected between a reset switch
304
and analog ground V
AG
218
. (Alternatively, analog ground V
AG
218
can be replaced by a first supply voltage “V
SS
”.) Preferably, bistable pair
302
comprises a first NMOSFET (n-channel Metal Oxide Semiconductor Field Effect Transistor) “M
1
”
306
and a second NMOSFET “M
2
”
308
. Ideally, M
1
306
and M
2
308
are matched transistors. Preferably, each of M
1
306
and M
2
308
has a gain greater than one. However, bistable pair
302
can function if the product of the individual gains of M
1
306
and M
2
308
(i.e., the loop gain) is greater than one. The gate terminal of M
2
308
is connected to the drain terminal of M
1
306
at a first port “N
4
”
310
. The gate terminal of M
1
306
is connected to the drain terminal of M
2
308
at a second port “N
5
”
312
. The source terminals of M
1
306
and M
2
308
are together connected to analog ground V
AG
218
. In this configuration, M
1
306
and M
2
308
are said to be cross connected. Preferably, reset switch
304
comprises a third NMOSFET “M
3
”
314
. The source terminal of M
3
314
is connected to the drain terminal of one of M
1
306
or M
2
308
; the drain terminal of

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