High speed latch circuit

Details High speed latch circuit High speed latch circuit

2001-09-17

2002-10-29

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000

Reexamination Certificate

active

06472920

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to latch circuits for use as memory cells or in other data capture applications, and more particularly to techniques for improving the performance of such latch circuits.
BACKGROUND OF THE INVENTION
Latch circuits are commonly used in data capture applications and may be implemented as or in conjunction with conventional data capture elements such as memory cells or flip-flops. There are many different types of latch circuits known in the art. Examples of conventional latch circuits are described in M. Afghani, “A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applications,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 2, pp. 247-254, February 1996, S. J. Lovett et al., “Yield and Matching Implications for Static RAM Memory Array Sense-Amplifier Design,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, pp. 1200-1204, August 2000, and J. -C. Kim et al., “CMOS sense amplifier-based flip-flop with two N-C
2
MOS output latches,” Electronics Letters, Vol. 36, No. 6, pp. 498-500, Mar. 16, 2000, all of which are incorporated by reference herein.
A significant problem with conventional latch circuits such as those described in the above-cited references is excessive propagation delay. For example, a conventional latch circuit configured to operate as a memory cell will generally require an input transmission gate in order to allow data to be introduced into the cell. Such a gate introduces a substantial propagation delay, and thus limits the speed at which the latch circuit can operate.
A related problem is unduly long set-up and hold time requirements. The set-up time refers generally to the period of time that the data must maintain a particular logic level at a latch circuit input prior to clocking, while the hold time refers to the amount of time that the data must remain at the particular level at the circuit input after clocking. The minimum requirements for the set-up and hold times must be satisfied in order for the particular data level to be reliably captured by the latch circuit. Unduly long set-up and hold time requirements therefore further limit the speed at which the latch circuit can operate.
The propagation delay problem and related set-up and hold time problem are typically attributable to excessive parasitic capacitance in the latch circuit. Such parasitic capacitance may be a function of the layout of the circuit, e.g., the manner in which the latch circuit is configured to accommodate requirements such as the above-noted input transmission gate.
In view of the foregoing, it is apparent that a need exists for an improved latch circuit that exhibits reduced propagation delay and set-up and hold time requirements, and thus a higher speed of operation.
SUMMARY OF THE INVENTION
The present invention meets the above-identified need by providing improved latch circuits that can operate with lower propagation delay and set-up and hold time requirements, and thus at a higher speed, than the conventional circuits mentioned above.
In accordance with one aspect of the invention, a latch circuit comprises at least one set of cross-coupled transistor devices arranged between an upper supply terminal of the circuit and a lower supply terminal of the circuit. In addition, a first input transistor device is coupled in parallel with a first one of the transistor devices of the set of cross-coupled transistor devices, and a second input transistor device is coupled in parallel with a second one of the transistor devices of the set of cross-coupled transistor devices. The first and second input transistor devices are adapted for application of respective uncomplemented and complemented inputs thereto during an initialization mode of the latch circuit. Uncomplemented and complemented output signals are generated at corresponding output terminals associated with the set of cross-coupled transistor devices during an evaluation mode of the latch circuit.
In accordance with another aspect of the invention, the latch circuit may be implemented as a master in a master-slave configuration having additional slave circuitry so as to provide a tradeoff between operating speed and a desired set-up and hold time window.
As noted previously, a latch circuit in accordance with the invention generally exhibits reduced propagation delay and set-up and hold times relative to conventional circuits. Another significant advantage of a latch circuit in accordance with the invention is that such a circuit can be configured to exhibit an improved power supply rejection ratio (PSRR), and thus can detect smaller input voltages than would otherwise be possible using conventional circuits.


REFERENCES:
patent: 4486673 (1984-12-01), Koike
patent: 4602167 (1986-07-01), Yukawa
patent: 4633098 (1986-12-01), Mahmud
patent: 5821791 (1998-10-01), Gaibotti et al.
patent: 6310501 (2001-10-01), Yamashita

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