High speed latch circuit

Details High speed latch circuit High speed latch circuit

1981-12-02

1984-04-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 307443, H03K 3356

Patent

active

044423659

ABSTRACT:
A latch circuit has first to fourth nodes. The first node is supplied with a logic signal and the second node is charged at a first potential. A potential at the third node is discharged to the second potential. The fourth node is charged to the first potential. This all happens during a first period, after which, and during a second period, a potential at the second node is transferred to the third node. An inverter transistor is responsive to a level of the logic signal at the first node for discharging a potential of the second node to a second potential when the logic signal level is in the first potential and for retaining the first potential of the second node when the logic signal level is in the second potential. A transfer between the fourth and the first nodes is responsive to the second potential at the third node for discharging the potential of the fourth node to the second potential. A true and a complement signals of a large amplitude are established at the fourth and second nodes.

REFERENCES:
patent: 3641360 (1972-02-01), Yao
patent: 3832578 (1974-08-01), Nomiya et al.
patent: 3846643 (1974-11-01), Chu et al.
patent: 4149099 (1979-04-01), Nagami
patent: 4216389 (1980-08-01), Carter

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