High-speed ISA bus control system for changing command cycle exe

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Details

395822, 395823, 395825, 395829, 395858, 395287, G06F 1300

Patent

active

056258470

ABSTRACT:
A system controller is provided with an ISA bus controller that executes a command cycle at a speed complying with the standards for ISA buses and a high-speed bus controller that executes a command cycle at a higher speed. When an I/O device that can operate at higher speeds than that of the ISA bus for a PCMCIA controller and IDE interface, a high-speed bus controller is used in place of the ISA bus controller. The high-speed bus controller executes a command cycle at a speed corresponding to the performance of the addressed I/O device. When a busy signal (an inactive IORDY signal) indicating that data transfer is not in time is outputted from the I/O device side, the cycle width of the command is lengthened. There are a synchronous sampling mode and an asynchronous sampling mode for the IORDY signal. The cycle from when IORDY goes off until the command goes off is set in a programmable manner.

REFERENCES:
patent: 5280587 (1994-01-01), Shimodaira et al.
patent: 5386517 (1995-01-01), Sheth et al.
patent: 5465333 (1995-11-01), Olnowich
patent: 5469555 (1995-11-01), Ghosh et al.

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