Electricity: power supply or regulation systems – In shunt with source or load – Using a three or more terminal semiconductive device
Reexamination Certificate
2000-01-31
2001-08-28
Sterrett, Jeffrey (Department: 2838)
Electricity: power supply or regulation systems
In shunt with source or load
Using a three or more terminal semiconductive device
C323S271000, C323S282000
Reexamination Certificate
active
06281665
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an internal voltage generating circuit for generating voltages used in, for example, a semiconductor memory device, and more particularly to an internal voltage generating circuit for generating different voltages.
In a nonvolatile semiconductor memory, such as a flash EEPROM, several types of voltages differing in level are applied to a memory cell, depending on the operation, such as a read operation, a program (write) operation, or an erase operation.
FIG. 1
shows the relationship between a series of operations in a nonvolatile semiconductor memory and the voltages applied to the control gate of a memory cell in the respective operations. As shown in
FIG. 1
, in addition to a read operation, a program (write) operation, and an erase operation, a verify operation is performed after a program or erase operation to cause the threshold value of the memory cell to converge in a certain range in the nonvolatile semiconductor memory.
Furthermore, to sense the overerased state after the data in the selected block in a memory cell array has been erased all at once, an overerase verify operation is performed using an overerase verify voltage for sensing an overerased cell. When an overerased cell has been sensed in the overerase verify operation, the overerased cell is subjected to weak programming (or a weak write operation). The weak programming is a method of controlling the threshold distribution of the cell into a narrow range of 0.5 to 1.0V. In the method, writing is done by changing the voltage applied to the control gate of the cell little by little. Specifically, when an erased cell has been sensed in an overerase verify operation, the overerased cell is subjected to weak programming at a first gate voltage. Thereafter, the threshold value of the cell is verified again. If the threshold value of the cell has not shifted to the target range of threshold value distribution, the cell is subjected to weak programming again at a voltage higher than the first gate voltage by a voltage of &Dgr;V. Repeating such an operation causes the threshold voltage of the cell to converge into the target range of threshold value distribution.
As described above, the nonvolatile semiconductor memory requires many voltages of different levels according to various types of operations.
In recent years, nonvolatile semiconductor memory devices have been designed to use a single power source. For this reason, the aforementioned various types of voltages used in a nonvolatile semiconductor memory are generated at a voltage generating circuit provided in a chip. The voltage generating circuit is composed of a booster circuit for boosting a supply voltage supplied from the outside and an internal voltage generating circuit for generating an internal voltage of a desired level from the output voltage of the booster circuit.
FIG. 2
shows an internal voltage generating circuit disclosed in Japanese Patent Application No. 8-162753 (Jpn. Pat. Appln. KOKAI Publication No. 10-011987). The internal voltage generating circuit, which is a voltage generating circuit of a so-called voltage-summing type, is capable of generating a voltage of a desired level according to the digital signal applied to a decoder. Specifically, in
FIG. 2
, a resistance string RS is composed of resistances R
0
to R
15
connected in series. The resistance string RS is connected via resistance Rstd to the ground. Switches S
0
to S
15
are connected to the junction nodes of an output node N
1
and the respective resistances R
0
to R
15
. The switches S
0
to S
15
are selectively turned on by the output signal of a decoder
17
to which digital signals A
0
, A
1
, A
2
, and A
3
are supplied. Differential amplifiers
11
and
12
compare the voltage at node N
2
to which the resistance string RS and resistance Rstd are connected with a reference voltage Vref. When the voltage at node N
2
is lower than the reference voltage Vref, the differential amplifier
11
goes high at its output terminal. When the voltage at node N
2
is higher than the reference voltage Vref, the differential amplifier
12
goes high at its output terminal.
The gate of an n-channel MOS transistor
13
is connected to the output of the differential amplifier
11
and is controlled by the output signal of the differential amplifier
11
. A p-channel MOS transistor
14
is connected between a power supply terminal VPP and one end of the current path of the transistor
13
and supplies current to the transistor
13
. A p-channel MOS transistor
15
connected between the power supply terminal VPP and the output node N
1
, together with the transistor
14
, constitutes a current-mirror circuit. The transistor
15
pulls up the potential at the output node N
1
according to the output signal of the differential amplifier
11
. An n-channel MOS transistor
16
has its gate connected to the output terminal of the differential amplifier
12
and its current path connected between the output node N
1
and the ground. When the output signal of the differential amplifier
12
is at the high level, the transistor
16
turns on, pulling down the potential at the output node N
1
. A booster circuit (not shown) supplies a voltage boosted from an external supply voltage to the power supply terminal VPP.
With this configuration, when the switch is changed according to a digital signal and the potential at node N
2
is made lower than the reference voltage Vref, the output signal of the differential amplifier
11
goes to the high level and the output signal of the differential amplifier
12
goes to the low level. As a result, the transistor
13
turns on, the transistor
16
turns off, and the transistor
15
turns on. This causes the output node N
1
to be charged via the transistor
15
, raising the output voltage Vout. When the potential at the node N
2
has become higher than the reference voltage Vref as a result of the rise of the output voltage Vout, the charging of the output node N
1
is stopped.
In addition, when the switch is changed according to the digital signal and the potential at the node N
2
is made higher than the reference voltage Vref, the output signal of the differential amplifier
11
goes to the low level and the output signal of the differential amplifier
12
goes to the high level. As a result, the transistor
13
turns off, the transistor
16
turns on, and the transistor
15
turns off. This causes the output node N
1
to be discharged via the transistor
16
, reducing the output voltage Vout. When the potential at the node N
2
has become lower than the reference voltage Vref as a result of the drop of the output voltage Vout, the discharging of the output node N
1
is stopped.
Although the internal voltage generating circuit can generate a required voltage, it has the following problem: as the number of output voltages increases, the number of resistances constituting the resistance string RS, the number of switches, and the number of decoders increase and therefore the area of the circuit increases. For example, when the number of output voltages is needed to be 32, 32 resistances are needed for the resistance string RS and 32 switches are required to switch these resistances. Furthermore, 32 5-bit decoders
17
for decoding a 5-bit digital signal are necessary to control the switches.
In general, when the number of output voltages is 2
N
, 2
N
resistances are required and 2
N
N-input decoders for decoding an N-bit digital signal are needed. As the value of N increases, the number of elements, including decoders and resistances, increases sharply and the area the pattern of those elements occupy in the chip increases, which makes the circuit design difficult. Moreover, the flexibility in changing the pattern decreases for variations in the value of resistance caused in the manufacture, which makes it difficult to change the design to adjust the value of resistance. Consequently, fine adjustment of the output voltage cannot be made.
To overcome the problem in the voltage-summing voltage ge
Kuriyama Masao
Miyaba Takeshi
Tanzawa Tooru
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Sterrett Jeffrey
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