High-speed internal interconnection technique for integrated cir

Details High-speed internal interconnection technique for integrated cir High-speed internal interconnection technique for integrated cir

1994-08-24

1997-03-25

Teska, Kevin J.

Boots, shoes, and leggings

H02B 120

Patent

active

056151268

ABSTRACT:
Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area. One aspect of the invention is directed to using auto-routing switching techniques for combining signals. Another aspect is directed to applying these combining/expanding techniques to the integrated circuit design process.

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Microsoft Press- Computer Dictionary Second Edition, 1994.

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