High-speed interface for a programmable device

Details High-speed interface for a programmable device High-speed interface for a programmable device

2006-02-14

2010-06-01

Trost, IV, William (Department: 2472)

Pulse or digital communications

Transceivers

C370S545000, C375S354000

Reexamination Certificate

active

07729415

ABSTRACT:
A high-speed interface for implementation in a programmable device such as, e.g., a programmable logic device (“PLD”) is described. Multi-gigabit transceivers of the PLD provide transmit and receive lock signals and have inputs for reference transmit and receive clock signals. One of the multi-gigabit transceivers provides a first transmit clock signal, a first receive clock signal, and a second receive clock signal. A data rate converter fractionally multiplies a second transmit clock signal to provide the reference transmit clock signal. A skew synchronization block obtains respective transmit and receive lock signals from the multi-gigabit transceivers and provides respective receive and transmit synch adjustment signals to the multi-gigabit transceivers. Synchronous operation of the multi-gigabit transceivers in receive and transmit directions is adjusted with receive and transmit synch adjustment signals to maintain lane-to-lane skew for the high-speed interface within a target range.

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Serdes Framer Interface Level(SFI-4) Phase 2: Implementation Agreement OIF-SFI4-02.0.
Voegele, Kevin et al., “SERDES Framer Interface Level 4 (SFI-4) Phase 2: Implementation Agreement for 10 Gb/s Interface for Physical Layer Devices”, OIF-SF14-02.0, Sep. 12, 2002, pp. 1-31, available from The Optical Internetworking Forum, 39355 California Street, Suite 307, Fremont, CA 94538.

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