High-speed interface circuit for semiconductor memory chips...

Details High-speed interface circuit for semiconductor memory chips... High-speed interface circuit for semiconductor memory chips...

2007-02-27

2007-02-27

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S219000

Reexamination Certificate

active

11152769

ABSTRACT:
A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core. The second interface circuit section is connectable to a read data bus and includes a transparent read data re-driver/transmitter path for transmitting and re-driving received serial read data to a succeeding semiconductor memory chip and a main read signal path for inserting the parallel-to-serial converted read data from the memory core into the received serial read data stream, synchronizing the parallel-to-serial converted read data with the reference clock signal and providing the serialized read data stream to a serial read data input terminal of a corresponding second interface circuit section of a succeeding same memory chip or to a memory controller.

REFERENCES:
patent: 6108745 (2000-08-01), Gupta et al.
patent: 7123497 (2006-10-01), Matsui et al.

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