High speed interconnection network for a cluster of processors

Details High speed interconnection network for a cluster of processors High speed interconnection network for a cluster of processors

1982-03-01

1984-09-04

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1516

Patent

active

044701144

ABSTRACT:
A high speed interconnect network for a relatively large number of processors from as few as five to a hundred or more where the information transfers are serial-by-byte in a time multiplexed manner so that when one or more processors is ready to transmit, there will be an information byte being transmitted every clock time. A bus arbiter controls access to a local bus in a round-robin fashion when one or more than one processor is requesting access to the local bus. The bus arbiter also serves for connection to an overall global loop of bus arbiters each of which has a local bus and a plurality of individual processors.

REFERENCES:
patent: 3916108 (1975-10-01), Schwartz
patent: 4402040 (1983-08-01), Evett

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