High-speed integrated circuit testing with JTAG

Details High-speed integrated circuit testing with JTAG High-speed integrated circuit testing with JTAG

1991-04-26

1994-10-11

Beausoliel, Jr., Robert W.

Excavating

371 221, H04B 1700

Patent

active

053553691

ABSTRACT:
The use of the JTAG port provides for boundary scan testing of integrated circuits, thereby allowing for the testing of IC's after they have been mounted into a circuit board. However, the conventional JTAG scheme is limited as to speed, since both the input and output vectors must be serially shifted in and out of I/O buffers along the chip boundaries. The present invention speeds the testing of high-speed core logic circuitry by transferring the test program to a special test data register, which downloads the program to the logic circuitry under test, and uploads the results. This allows the core logic to perform the test at its normal operating speed, while still retaining compatibility with the JTAG standard for other tests.

REFERENCES:
patent: 4455661 (1984-06-01), Qureshi
patent: 4710927 (1987-12-01), Miller
patent: 4811345 (1989-03-01), Johnson
patent: 4945536 (1990-07-01), Hancu
patent: 5068783 (1991-11-01), Tanagawa et al.
Journal of Electronic Testing: Theory and Applications, "In Introduction to the Boundary Scan Standard; ANSI/IDDD Std. 1149.1" by Maunder et al. Mar., 1991, pp. 27-42.
Electronik, Feb. 2, 1989, Messen und Testen, "Verbesserte Prufbarkeit durch strukturierte ASIC-Designs" by Dr. Wolfgang Wach, pp. 31-36, English Abstract of French Patent 2643992.
Motorola Semiconductor Technical Data, DSP96002, by BR575/D, Technical Summary, "96-Bit General Purpose Floating-Point Digital-Signal Processor (DSP)" Motorola, Inc., 1988.
Texas Instruments TMS320C50 DSP Preview Bulletin, p. 4.
Texas Instruments TMS 320 Family Development Support Reference Guide Hardware Development Tools--TMS320 Emulator (XDS), pp. 5-17 to 5-32.
The Test Access Port and Boundary Scan Architecture, Colin M. Maunder and Rodham E. Tulloss, IEEE Computer Society Press Tutorial, 1990 IEEE, pp. 33 through 77.
Publication: Digital Signal Processing: Technology and Applications, Title: TMS320C50-The Next Generation 35NS Fixed-Point Digital Signal Processor, Author: C Marven, Texas Instruments Ltd., Journal Date: Oct. 19, 1989, Page No.: 5.1/1-8.

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