Boots – shoes – and leggings
Patent
1986-11-10
1988-12-13
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 1518, G06F 15347
Patent
active
047915595
ABSTRACT:
An instruction flow control system includes an instruction buffer for receiving stored program instructions. A program address generator signals the instruction buffer for fetching the instructions. A translate RAM decodes the fetched instructions and a translate map gate array generates an address to the translate RAM in response to mapped and remapped instructions being fetched from the instruction buffer. The map gate array looks at an operation code included in the instructions and determines if remapping is required. If so, an address is generated including a constant providing a block of specific addresses and a variable providing a specific address within the block. The mapped instruction includes a seven bit operation code field and, in response to a mapped instruction being fetched, all of the seven bits are mapped directly to the translate RAM address. The address generated by the map gate array includes a most significant address bit and, in response to a remapped instruction being fetched, the gate array forces the most significant bit to 1 and generates an address by selecting a unique variable of the remapped instruction.
REFERENCES:
patent: 4462073 (1984-07-01), Grondalski
patent: 4591972 (1986-05-01), Guyer et al.
Anderson Lawrence E.
Harkcom Gary V.
Marhoefer L. J.
Scott T. J.
Sowell John B.
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