High speed instruction alignment unit for aligning variable byte

Details High speed instruction alignment unit for aligning variable byte High speed instruction alignment unit for aligning variable byte

1997-05-28

1998-05-26

Lall, Parshotams S.

395389, G06F 930

Patent

active

057581142

ABSTRACT:
An instruction alignment unit is provided which transfers a fixed number of instructions from an instruction cache to each of a plurality of decode units. The instructions are selected from a quantity of bytes according to a predecode tag generated by a predecode unit. The predecode tag includes start-byte bits that indicate which bytes within the quantity of bytes are the first byte of an instruction. The instruction alignment unit independently scans a plurality of groups of instruction bytes, selecting start bytes and a plurality of contiguous bytes for each of a plurality of issue positions. Initially, the instruction alignment unit selects a group of issue positions for each of the plurality of groups of instructions. The instruction alignment unit then shifts and merges the independently produced issue positions to produce a final set of issue positions for transfer to a plurality of decode units.

REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5113515 (1992-05-01), Fite et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5214763 (1993-05-01), Blaner et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5463748 (1995-10-01), Schwendinger
patent: 5513330 (1996-04-01), Stiles
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, October 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.

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