High speed initialization system for RAM devices using JTAG loop

Details High speed initialization system for RAM devices using JTAG loop High speed initialization system for RAM devices using JTAG loop

1996-01-05

1998-10-13

Canney, Vincent P.

Excavating

39518306, G06F 1100

Patent

active

058223347

ABSTRACT:
A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.

REFERENCES:
patent: 5526365 (1996-06-01), Whetsel

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