High speed incrementer with array method

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36471603, G06F 750, G06F 738

Patent

active

058779728

ABSTRACT:
A high-speed incrementer array for incrementing a data input value by a binary one, wherein the data input value comprises a plurality of input bit values. The incrementer array includes a plurality of word lines, bit-line pairs, and sense amplifiers. The input bit values are received as a plurality of complement input signals and a plurality of true input signals. The complement input signals are transmitted on the plurality of word lines that form the rows of the array. Each one of plurality of bit-line pairs is located in a respective column of the array and is coupled to particular ones of the word lines in the rows of the array. Each one of the plurality of sense amplifiers is coupled to a respective bit-line pair for sensing a voltage difference between the bit-line pair, such that the bit-line pair and the sense amplifier perform a logical NOR of the complement input signals to produce a NOR output. Each one of the plurality of exclusive-or gates is coupled to a respective NOR output and to a particular one of the true input signals for generating an incremented output signal.

REFERENCES:
patent: 3989940 (1976-11-01), Kihara
patent: 4153939 (1979-05-01), Kudou
patent: 4280190 (1981-07-01), Smith
patent: 4417315 (1983-11-01), Russell
patent: 4417316 (1983-11-01), Best
patent: 4700325 (1987-10-01), Ware
patent: 4953115 (1990-08-01), Kanoh
patent: 4972105 (1990-11-01), Burton et al.
patent: 5003202 (1991-03-01), Keida
patent: 5221867 (1993-06-01), Mitra et al.
patent: 5398198 (1995-03-01), Mahant-Shetti et al.
IBM Tech Discl. Bull. vol. 25 No. 1 Jun. 1982, pp. 71-73, "FET DRAM Look-Ahead Address Incrementer".
IBM Tech Discl. Bull. vol. 25 No. 1 Jun. 1982, pp. 75-76, "High-Speed Incrementer Using Transfer Gates".
IBM Tech Discl. Bull. vol. 11 No. 3 Aug. 1968, pp. 297-298, "incrementer-Decrement Logic".
J.W. Jones and J.C. Logue, "Array Logic with Dynamic Bit Selection and 4-State Crosspoint Conditioning", IBM Technical Disclosure Bulletin, vol. 17 No. 3 Aug. 1974.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High speed incrementer with array method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed incrementer with array method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed incrementer with array method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-428728

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.