High speed incrementer/decrementer

Details High speed incrementer/decrementer High speed incrementer/decrementer

2000-05-12

2003-12-16

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06665698

ABSTRACT:

BACKGROUND OF THE INVENTION
In standard electronic circuits that include logic functionality, such as microprocessors that perform simple address incrementing, adders are typically used to perform the incrementing. However, the use of adders to perform simple incrementing is typically quite inefficient since a full adder requires more circuitry, and therefore more chip area and power, and is also typically slower than a simple incrementer. Accordingly, a need exists for a high speed incrementer (and decrementer) that can perform the requirements of an incrementer with less power and in a smaller amount of space.
SUMMARY OF THE INVENTION
A high speed incrementer/decrementer design is presented that is easy to implement, requires less chip space and less power, and is faster than prior art adders. In accordance with the design of the invention, carries and sums are computed using propagate, generate, and kill signals that are derived from the incrementer inputs. By setting one input to “0” and the carry-in to “1”, the adder is used as an incrementer. In the design of the invention, a decision is made whether to complement the input or not. The design also allows decrementing and supports both unsigned and 2's complement number representations.


REFERENCES:
patent: 3989940 (1976-11-01), Kihara
patent: 4153939 (1979-05-01), Kudou
patent: 5018094 (1991-05-01), Fischer et al.
patent: 5384724 (1995-01-01), Jagini
“MOSFET Look-Ahead Bit Incrementer/Decrementer”, IBM Technical Disclosure Bulletin, vol. 28, No. 2, Jul. 1985, pp. 741-774.*
“Increment Decrement Logic”, IBM Technical Disclosure Bulletin, vol. 11, No. 3, Aug. 1968, pp. 297-298.

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