High speed I-O loopback testing with low speed DC test...

Details High speed I-O loopback testing with low speed DC test... High speed I-O loopback testing with low speed DC test...

2007-04-03

2007-04-03

Ghebretinsae, Temesghen (Department: 2611)

Pulse or digital communications

Testing

C370S241000, C370S249000

Reexamination Certificate

active

10193131

ABSTRACT:
A loopback circuit for testing low and high frequency operation of integrated circuit transmitter and receiver components. First and second resistors forming a first branch of the circuit are series-connected between first and second circuit ports. Third and fourth resistors forming a second branch of the circuit are series-connected between third and fourth circuit ports. A DC isolator is connected between the first and second branches. At lower frequencies, the two branches are DC-isolated, enabling ATE-measurement of the transmitter's output drive level independently of the receiver, continuity testing of ESD protection structures, etc. At higher frequencies, the transmitter's output signal is split into three portions, each of which is attenuated by a selected amount. One of the attenuated signal portions is applied to the receiver to test the receiver's sensitivity, independently of possible excess resiliency in the transmitter's output drive level.

REFERENCES:
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patent: 4743857 (1988-05-01), Childers
patent: 5479098 (1995-12-01), Yokoyama et al.
patent: 5787114 (1998-07-01), Ramamurthy et al.
patent: 5953372 (1999-09-01), Virzi
Howard Johnson and Martin Graham, “High Speed Digital Design: A Handbook of Black Magic,” Prentice Hall, Inc. Upper Saddle River, NJ, pp. 236, 1993.

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