High-speed, high pin-out LSI chip package

Details High-speed, high pin-out LSI chip package High-speed, high pin-out LSI chip package

1982-12-29

1985-02-05

Kucia, R. R.

Electricity: electrical systems and devices

Miscellaneous

174 34, 174 36, 174 685, H05K 114

Patent

active

044981228

ABSTRACT:
A high-speed, high pin-out chip carrier package (10) for interconnecting at least one LSI or VLSI chip to a circuit pack is disclosed. The package includes a ground plane (19), a power plane (20), and at least one signal layer (15, 16, 17, 18) containing plural conductors therethrough. Layers (85) of dielectric material separate adjacent conductive layers, (15, 16, 17, 18, 19, 20). By controlling, in design, the width of each signal conductor and its distance to the nearest ground (19) or power plane (20), the package is impedance-matched to the circuit pack. Plural plated-through holes (21) are disposed through the package for electrically interconnecting the signal conductors, the ground plane (19), and the power plane (20) to the circuit pack, and are arranged in a pattern to reduce inductive noise.

REFERENCES:
patent: 3568000 (1971-03-01), D'Aboville
patent: 3643201 (1972-02-01), Harwood
patent: 3740678 (1973-06-01), Hill
patent: 3867759 (1975-02-01), Siefker
patent: 4047132 (1977-09-01), Krajewski
patent: 4353040 (1982-10-01), Krumm et al.
Helmut E. Brenner, Use a Computer to Design Suspended-Substrate ICs, Microwaves, Sep. 1968, pp. 38 to 43 relied on, copy in 333-238.
A. J. Rainal, Transmission Properties of Various Styles of Printed Wiring Boards, Bell System Tech. J., vol. 58 #5, Jun. 1979, pp. 995 to 1025.

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