High speed/high drive CMOS output buffer with inductive bounce s

Details High speed/high drive CMOS output buffer with inductive bounce s High speed/high drive CMOS output buffer with inductive bounce s

1986-12-29

1988-11-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307585, 307263, H03K 19003

Patent

active

047852011

ABSTRACT:
An output buffer is disclosed which employs a first pair of transistors connected in an (N-channel over P-channel) totem pole configuration, a second pair of transistors connected in a (P-channel over N-channel) totem pole configuration in parallel with the first pair of transistors, and a pair of inverters connected to delay the drive to the second pair of transistors.

REFERENCES:
patent: 3846822 (1974-11-01), Riley et al.
patent: 4567378 (1986-01-01), Raver
patent: 4587445 (1986-05-01), Kanuma
patent: 4609834 (1986-09-01), Gal
patent: 4622482 (1986-11-01), Ganger
patent: 4638187 (1987-01-01), Boler et al.

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