High speed high density dynamic address translator

Details High speed high density dynamic address translator High speed high density dynamic address translator

1986-07-21

1989-03-14

Harkcom, Gary V.

Static information storage and retrieval

Associative memories

Ferroelectric cell

365231, 364900, G11C 1500, G06F 1210

Patent

active

048130028

ABSTRACT:
A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time then required for a single CAM memory. The results are logically combined with in the RAM which, in response to a match condition, delivers the results of the translation as an output.

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Weste, Principles of CMOS VLSI Design, 1985.

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