High-speed, high-capacity, fault-tolerant error-correcting stora

Details High-speed, high-capacity, fault-tolerant error-correcting stora High-speed, high-capacity, fault-tolerant error-correcting stora

1989-02-27

1990-07-17

Smith, Jerry

Excavating

3642464, 3642663, 3642685, 371 101, G06F 1110, G06F 1116

Patent

active

049425790

ABSTRACT:
A storage system for dynamic and trasparent error correction has a number of first individual storage devices for information and a second individual storage device for error code bits that are used to correct the information when one of the storage devices detects an error. Each error code bit is generated from the information at respective bit positions across the first storage devices. Storage device controllers are connected between a user CPU interface and respective storage devices for operating them concurrently. The interface includes an interface CPU for controlling the storage device controllers and translating the interface convention of user CPU requests into the interface convention of the storage devices. A buffer memory is connected to data surface associated with the respective storage devices. The interface CPU includes logic for immediately acknowledging a write to the associated storage device upon the data being placed in the buffer memory. The interface CPU also includes logic for checking data in the buffer memory and indicating it as having been read from an associated storage device without an actual read, whereby the buffer memory acts as a cache.

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Kim, "Synchronized Disk Interleaving", IEEE Trans. on Computers, vol. C-35, No. 11, Nov. 1986.

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