High speed hardware multiplier for fixed floating point operands

Details High speed hardware multiplier for fixed floating point operands High speed hardware multiplier for fixed floating point operands

1983-07-21

1986-06-10

Thomas, James D.

Boots, shoes, and leggings

364738, 364757, G06F 752, G06F 1100

Patent

active

045946795

ABSTRACT:
A high speed multiplier unit for multiplying both fixed point and floating point operands is disclosed and claimed. This multiplier unit is a system level functional unit which allows floating point and fixed point operations to be performed directly. In addition to multiplication, the multiplier unit performs exponent calculation, post-normalization, and error detection. The multiplier unit also provides for overlapped loading of operands.

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R. K. Richards, Arithmetic Operations in Digital Computers, pp. 136-140; 160-161 (1955).

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