High speed gallium arsenide latch using depletion mode logic

Details High speed gallium arsenide latch using depletion mode logic High speed gallium arsenide latch using depletion mode logic

1991-02-27

1992-06-09

LaRoche, Eugene R.

Electric lamp and discharge devices: systems

Pulsating or a.c. supply

Transformer in the supply circuit

307571, 307584, H03K 326, H03K 19017

Patent

active

051210355

ABSTRACT:
A non-inverting gallium arsenide depletion mode latch circuit is responsive to high and low input data, and to clock pulses from a clock having high and low pulses for loading data and for translating data from the input to the output in a single gate delay. The circuit includes a pair of pull-up FETs having their conduction paths connected in parallel with an output node in circuit with the FETs for output data. A positive feedback path is enabled from one of the FETs for reinforcing the data at the output node. The one FET enables the feedback path during clock pulses in the low direction, while the other FET applies data to the node during high clock pulses. Data input FETs enable and disable the other FET in accordance with the input data and selective clock pulses, while a clock pulse input FET enables and disables the one FET in accordance with the clock pulses.

REFERENCES:
patent: 4521703 (1985-06-01), Dingwall
patent: 4707808 (1987-11-01), Heimbigner
patent: 4764897 (1988-08-01), Kameyama et al.
patent: 4883985 (1989-11-01), Katsu et al.
patent: 4939390 (1990-07-01), Coe
patent: 4975596 (1990-12-01), Thomas et al.
patent: 5032741 (1991-07-01), Smith

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