High speed gain amplifier and method in ADCs

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C341S161000, C327S377000, C327S091000

Reexamination Certificate

active

07042383

ABSTRACT:
An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.

REFERENCES:
patent: 6166675 (2000-12-01), Bright
patent: 6400301 (2002-06-01), kulhalli et al.
patent: 6466153 (2002-10-01), Yu

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High speed gain amplifier and method in ADCs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed gain amplifier and method in ADCs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed gain amplifier and method in ADCs will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3604555

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.