High speed full adder using complementary input-output signals

Details High speed full adder using complementary input-output signals High speed full adder using complementary input-output signals

1987-10-26

1989-09-26

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

048706094

ABSTRACT:
The operation speed of a full adder is increased by avoiding the necessity of forming the inverse signal for adder operation and deleting the time required for passing through an inverter.

REFERENCES:
patent: 4601007 (1986-07-01), Uya et al.
patent: 4709346 (1987-11-01), Henlin
patent: 4713790 (1987-12-01), Kloker et al.
Henlin et al., "A 25 MHz 16 Bit x 16 Bit Pipelined Multiplier" CH2080-0/84/0000/0417$01.00 1984, IEEE, pp. 417-422.
Heller et al., "Custom and Semi-Custom Design Techniques" 1984 IEEE International Solid-State Circuits Conference, Feb. 22, 1984, pp. 16-17.

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