High speed full adder and method

Details High speed full adder and method High speed full adder and method

1991-04-29

1992-12-29

Malzahn, David H.

Boots, shoes, and leggings

364786, G06F 750

Patent

active

051757036

ABSTRACT:
A high-speed current mode 2-bit full adder using ripple carry with two full adders using three-levels of series gating, a bandgap reference voltage generator, two sum out buffers, and a carry out buffer. The method for the addition of an input carry bit and two 2-bit input bytes uses a logic circuit satisfying Boolean expressions SUM=ABC+AB'C'+A'B'C+A'BC' and C.sub.OUT =BC+AC+AB, where first 2-bit input byte A.sub.1 B.sub.1 and carry in byte C.sub.IN produce SUM equal to first bit sum S.sub.1 and an intermediate carry out bit at two voltage levels, C.sub.2, and C.sub.3 to facilitate processing. Second 2-bit byte A.sub.2 B.sub.2 and an intermediate carry out bit at C.sub.2 and C.sub.3, input to the bit 2 full adder, produce SUM equal to secondd bit sum S.sub.2 and final carry out bit C.sub.OUT. Each sum function uses only one current source to reduce components, lower power consumption, and improve efficiency.

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Menon et al, "A High Performance Parallel 16.times.16 Bit Bipolar Multiplier Using Standard Cell Design Methodology", IEEE 1987 Bipololar Circuits and Technology Meeting Sep. 21-22, 1987 Minneapolis, Minn. pp. 105-107.

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