High speed frame buffer refresh apparatus and method

Details High speed frame buffer refresh apparatus and method High speed frame buffer refresh apparatus and method

1983-10-31

1987-08-18

Williams, Jr., Archie E.

Boots, shoes, and leggings

340750, 340799, G06F 3153

Patent

active

046881905

ABSTRACT:
A computer memory architecture is most advantageously used in conjunction with a digital computer, to provide an improved high speed graphics display capability. Data representative of digital images to be displayed is generated and/or manipulated by a display processor and stored within a selected portion of the display processor's main memory. Subsequent modifications to the stored image are effectuated by the display processor reading the data from its main memory, performing appropriate operations on the data, and writing the data back into the main memory. Updated images are transferred to an buffer memory which sequentially stores the images in the order in which they were updated by the display processor. Data representative of an updated image is then transferred to the display frame buffer of the particular display system for subsequent display. Data is transferred from the buffer memory to the frame buffer during periods when the frame buffer is not refreshing the display.

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"A Random-Access Video Frame Buffer", James T. Kaziya, Ivan E. Sutherland and Edward C. Cheadle; Proceedings of the Conference on Computer Graphics, Pattern Recognition, and Data Structure, May 14-16, 1975.

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