Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1992-02-04
1993-02-23
Sikes, William L.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
3072723, 307279, H03K 3289, H03K 3356
Patent
active
051893150
ABSTRACT:
A flip flop circuit comprises a master latching circuit having a first transmission gate responsive to a clock signal and the complementary clock signal for transferring a data bit to a first positive feedback loop, and a slave latching circuit having a second transmission gate responsive to the clock signal and the complementary clock signal and complementarily shifted between on and off states with respect to the first transmission gate for transferring a data bit to a second positive feedback loop, wherein a buffer circuit is coupled between the first positive feedback loop and the first transmission gate so that the master flip flop circuit is free from influence of the slave flip flop circuit, thereby allowing a circuit designer to shrink set-up time margin.
REFERENCES:
patent: 4613773 (1986-09-01), Koike
patent: 4794276 (1988-12-01), Sasada et al.
patent: 4843254 (1989-06-01), Motegi et al.
patent: 4939384 (1990-07-01), Shikata et al.
patent: 5017808 (1991-05-01), Ueno et al.
patent: 5027382 (1991-06-01), Hiroe et al.
Research Disclosure, "CMOS L1L2 Latch Which Compares Bipolar Levels"; Jul. 1991.
Cunningham Terry D.
NEC Corp.
Sikes William L.
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