High-speed error correcting random access memory system

Details High-speed error correcting random access memory system High-speed error correcting random access memory system

1982-07-19

1985-12-24

Atkinson, Charles E.

Excavating

371 3, G06F 1110

Patent

active

045610959

ABSTRACT:
A high speed error correcting random access memory system includes a circuit for generation of a plurality of parity bits from a predetermined combination of data bits of a data word being stored in a random access memory such that these parity bits are stored in memory along with said data bits, and for outputting the data word from said memory system, including correcting for any single bit error in the data word, by a circuit that generates a check word from the data word bits and parity word bits stored in the memory, whose state indicates if any of the data bits are in error, and, if so, proceeds to correct any such erroneous bit. The system also includes a circuit for inserting an erroneous bit of data in memory after the parity bits have been generated, to check operation of the check word generating and output data word correction circuit. The operation of the check word generating circuit can also be suspended so as to enable uncorrected data words to be output by the memory system.

REFERENCES:
patent: 4072853 (1978-02-01), Barlow et al.
patent: 4345328 (1982-08-01), White
patent: 4359771 (1982-11-01), Johnson et al.
patent: 4388684 (1983-06-01), Nibby, Jr. et al.
Blazejewski et al., Mechanism for Checking Parity and Error Checking, etc., IBM Technical Disclosure Bulletin, vol. 21, No. 12, May 1979, pp. 4871-4877.

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