High speed equalization in a memory

Details High speed equalization in a memory High speed equalization in a memory

1986-01-28

1987-12-08

Popek, Joseph A.

Static information storage and retrieval

Addressing

365203, G11C 800

Patent

active

047121971

ABSTRACT:
A memory is comprised of memory cells located at intersections of word lines and bit line pairs. The memory has a read mode in which data is read from a bit line pair selected by a column address. The data to be read is provided to bit line pairs by the memory cells which are coupled to a word line which has been selected to be enabled by a row address. In the write mode, data is written to a memory cell which is coupled to an enabled word line and which is coupled to a bit line pair into which data has been selected to be written. The pairs of bit lines are equalized in voltage in response to not only an address transition but also in response to a transition from the write mode to the read mode.

REFERENCES:
patent: 4355377 (1982-10-01), Sud et al.
patent: 4612631 (1986-09-01), Ochii
patent: 4636991 (1987-01-01), Flannagan et al.

Affiliated with

Also associated with

Rating

High speed equalization in a memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed equalization in a memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed equalization in a memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-25122