High-speed emitter-coupled logic buffer

Details High-speed emitter-coupled logic buffer High-speed emitter-coupled logic buffer

1990-12-11

1991-11-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 3072721, 307362, H03K 19096, H03K 1716

Patent

active

050650505

ABSTRACT:
An emitter-coupled logic (ECL) buffer circuit using two differential pairs of transistors to limit the output voltage of the buffer to ECL signal levels. A first differential pair of transistors couples the current from a first current source to load resistors in the buffer, thereby establishing the output voltage for the logical "low" output. The second differential pair couples the current from a second current source, having a current less than the current from the first current source, to the load resistors to establish the output voltage for the logical "high" output.

REFERENCES:
patent: 4868420 (1989-09-01), Itoh et al.
patent: 4912347 (1990-03-01), Morris
"Family Overview", F100K ECL Data Book, Fairchild, 1986, pp. 2-6 through 2-11.
"Bipolar Digital Gate Circuits", Analysis and Design of Digital Integrated Circuits, David A. Hodges, Horace G. Jackson, Copyright 1988, pp. 264 through 269.
"10113 Gate", Data Manual 1986, Signetics, ECL Products, Jan. 30, 1986, pp. 6-75 & 6-76.
"Key Components of the Fast Reduced Instruction Set Computer (FRISC) Employing Advanced Bipolar Differential Logic and Wafer Scale Multichip Packaging", IEEE 1988 Bipolar Circuits & Technology Meeting, H. J. Greub, J. F. McDonald, T. Creedon, Paper 1.1, pp. 19-22.

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