High speed elastic buffer with clock jitter tolerant design

Details High speed elastic buffer with clock jitter tolerant design High speed elastic buffer with clock jitter tolerant design

2008-04-29

2008-04-29

Orgad, Edan (Department: 2619)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S516000

Reexamination Certificate

active

07366207

ABSTRACT:
A receiver for high-speed indirect synchronous digital data transmission includes an elastic buffer receiving an incoming data stream containing embedded timing information preceding a data sequence, generating a recovered clock from the timing information, initially synchronizing the frequency of a local clock to the recovered clock, and accommodating subsequent drift between the recovered and local clocks across the duration of the data sequence while tolerating clock jitter. Received data is clocked into a FIFO buffer within the elastic buffer based on the recovered clock and read out based upon the local clock, with the buffer expanding or contracting by adjustment of an index to accommodate skew of greater than one clock period. Expansion or contraction of the FIFO buffer is disabled during periods when clock jitter is likely, such as periods immediately following an index change.

REFERENCES:
patent: 4823365 (1989-04-01), Loginov
patent: 5563891 (1996-10-01), Wang
patent: 6693918 (2004-02-01), Dallabetta et al.
patent: 6882661 (2005-04-01), Creedon et al.
patent: 6999480 (2006-02-01), Subrahmanyan et al.
patent: 2001/0016023 (2001-08-01), Roy et al.
patent: 2003/0227945 (2003-12-01), Braff et al.

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