High speed ECL to CMOS translator having reduced power consumpti

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 3072966, H03K 19092, H03K 1908

Patent

active

050121367

ABSTRACT:
A high speed voltage translator provides a CMOS output signal in response to an ECL input signal which is applied to an input stage coupled between first and second power supply conductors wherein the potential developed at the output of the input stage is independent of variations in the power supply voltage. The translating stage is coupled between said first and second power supply conductors and is responsive to the potential developed at the output of the input stage for conducting a predetermined current therethrough. A feedback signal proportional to the magnitude of the predetermined current flowing through the translating stage is generated to control the potential developed at the output of the input stage so as to maintain the predetermined current at a low value to reduce the power consumption of the voltage translator.

REFERENCES:
patent: 4456838 (1984-06-01), Taguchi et al.
patent: 4603268 (1986-07-01), Davis
patent: 4642483 (1987-02-01), Tomita
patent: 4644194 (1987-02-01), Birrittelca et al.
patent: 4825108 (1989-04-01), Burton et al.

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