High speed ECL output circuit having reduced power consumption

Details High speed ECL output circuit having reduced power consumption High speed ECL output circuit having reduced power consumption

1993-05-10

1995-04-11

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327108, 327542, G05F 110

Patent

active

054061369

ABSTRACT:
The output circuit according to the present invention includes a bipolar transistor (Q.sub.1), a resistance (R.sub.1) and a constant current source. The transistor (Q.sub.1) has its collector connected to a power supply node (V.sub.CC), its emitter connected to an output node (Do), and its base connected to the other end of the resistance (R.sub.1). The resistance (R.sub.1) has one end connected to the power supply node (V.sub.CC). The constant current source is connected between a power supply node (V.sub.EE) and the base of the transistor (Q.sub.1) and is turned on/off in response to an input signal (IN) to generate a current (I.sub.1) for bringing output into a low level only in the on state. The constant current source does not generate the current (I.sub.1) at the time of output of a high level, and causes the current (I.sub.1) to flow through the resistance (R.sub.1) only at the time of output of a low level. As a result, power consumption can be reduced.

REFERENCES:
patent: 4471241 (1984-09-01), Nagano
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patent: 5041743 (1991-08-01), Matsumoto
patent: 5173623 (1992-12-01), Chan et al.
patent: 5214328 (1993-05-01), Ohi
"A 10K-Gate 950-MHz CML Demonstrator Circuit Made with a 1-.mu.m Trench-Isolated Bipolar Silicon Technology", by Maurice P. Depey et al, IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 552-557.
"A 50-ps 7k-Gate Masterslice using Mixed Cells Consisting of an NTL Gate and and LCML Macrocell", by Haruhiko Ichino et al, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 202-207.

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