High speed ECL latch with clock enable

Details High speed ECL latch with clock enable High speed ECL latch with clock enable

1990-06-29

1992-01-07

Mis, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307467, 307240, 307254, H03K 1760, H03K 19086

Patent

active

050794523

ABSTRACT:
An ECL latch having a clock enable is provided with a first current source for the latch and a second current source for the clock enable. The latch alternates between a latch mode and a transparent mode under the control of a CLOCK signal. The clock enable operates to inhibit CLOCK signal control of the latch and holds the latch in the latch mode when an appropriate enable signal is applied to the clock enable. A current switch is provided to gate current from the second current source to the latch so that current from both current sources is gated to the latch during the transparent mode when the CLOCK signal controls latch operation. In this manner, the speed of operation of the latch during the transparent mode is increased. Thus, the latch will have an improved propagation delay to permit latch operation with a smaller clock period for a given supply current.

REFERENCES:
patent: 3906212 (1975-09-01), Poguntke
patent: 4408134 (1983-10-01), Allen
patent: 4540900 (1985-09-01), Early et al.
patent: 4551639 (1985-11-01), Takeda et al.
patent: 4560888 (1985-12-01), Oida
patent: 4607172 (1986-08-01), Frederiksen et al.
patent: 4626709 (1986-12-01), Mazumder et al.
patent: 4686394 (1987-08-01), Lam
patent: 4754173 (1988-06-01), Smith et al.
patent: 4777388 (1988-10-01), Widener
patent: 4900954 (1990-02-01), Franz et al.

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