High speed early/late discrimination systems and methods for...

Pulse or digital communications – Synchronizers

Reexamination Certificate

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C375S355000

Reexamination Certificate

active

07376211

ABSTRACT:
The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation and timing of clocks. The invention employs a differential analog circuit, using current steering logic, to process center and edge samples and identify an average operation of the clocks. The circuit can identify transitions between adjacent center/edge data samples and determine whether an identified transition is early or late for each bit in a set of consecutive bits of a received serial data stream.

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patent: 6370212 (2002-04-01), Nakai
patent: 6542015 (2003-04-01), Zhou et al.
patent: 6693985 (2004-02-01), Li et al.
patent: 6920622 (2005-07-01), Garlepp et al.
patent: 7076377 (2006-07-01), Kim et al.
patent: 2003/0198105 (2003-10-01), Yamaguchi et al.

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