High speed dynamic latch comparator

Details High speed dynamic latch comparator High speed dynamic latch comparator

1998-11-23

2000-11-07

Nuton, My-Trang

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 65, G01R 1900, G11C 700

Patent

active

061442313

ABSTRACT:
A dynamic latching comparator is provided for use with first and second signal input lines. The dynamic latching comparator includes latching circuitry having first and second pull-up devices connected, respectively, between first and second nodes and a high voltage source and first and second pull-down devices connected, respectively, between the first and second nodes and a ground. The first and second pull-down devices have gates connected, respectively, to the first and second input lines. A gate of the first pull-up device is cross-coupled to the second node. A gate of the second pull-up device is cross-coupled to the first node. The dynamic latching comparator also includes differential amplifier circuitry having third and fourth pull-down devices connected, respectively, between the first and second nodes and the ground. A gate of the third pull-down device is cross-coupled to the second node. A gate of the fourth pull-down device cross-coupled to the first node. The third and fourth pull-down devices have a transconductance therebetween equal to about half a transconductance between the first and second pull-down devices. With this configuration, high accuracy and high speed is achieved despite possible process variations while nevertheless lowering input capacitance and thereby permitting operation using reduced power.

REFERENCES:
patent: 5793551 (1998-08-01), Ngo et al.
patent: 5821792 (1998-10-01), Miwa
patent: 5854562 (1998-12-01), Toyoshima et al.
patent: 5936432 (1999-08-01), Oh et al.
patent: 5982692 (1999-11-01), Kattunire et al.
Article "A 10b, 20Msample/s, 35 mW Pipeline AD Converter", by Cho it al., IEEE, 1995 (7 pages).

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