High speed dynamic flip-flop system

Details High speed dynamic flip-flop system High speed dynamic flip-flop system

1976-12-27

1978-08-08

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

58 23AC, 307208, 307225C, 307265, 307279, 307200B, G04C 300, H03K 2330, H03K 3353

Patent

active

041048601

ABSTRACT:
A high speed dynamic CMOS flip-flop system having a master and a slave section each of which have a different total propagation delay. Asymmetrical clock signals are applied to the master and slave sections with one cycle portion of each clock signal turning on the master section and the other cycle turning on the slave section. Each cycle portion has a time duration substantially equal to the total propagation delay of its respective master and slave section. In this manner, the duty cycle of the clock signal cycle is matched to the ratio of the propagation delays of the master and slave sections.

REFERENCES:
patent: 3737746 (1973-06-01), Cielaszyk et al.
patent: 3757510 (1973-09-01), Dill
patent: 3812670 (1974-05-01), Nikaido et al.
patent: 3851189 (1974-11-01), Moyer
patent: 3958187 (1976-05-01), Suzuki et al.
patent: 3963946 (1976-06-01), Zajac
patent: 3984972 (1976-10-01), Yoshino
patent: 3986046 (1976-10-01), Wunner

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