High speed dynamic allocator for various length time slots

Details High speed dynamic allocator for various length time slots High speed dynamic allocator for various length time slots

1990-12-18

1991-08-13

Weldon, Ulysses

Communications: electrical

Continuously variable indicating

With meter reading

370 581, 370 841, H04Q 1100

Patent

active

050399861

ABSTRACT:
An improved multiplex controller circuit allows fast, on demand allocation of variable length time slots in a voice/data communications system. The controller circuit directly maps a triangular connection matrix into hardware, thereby providing hardware parallelism Each one of the coordinate points of the matrix is implemented with a flip-flop (L.sub.ij). The inputs of the flip-flops are provided by a Port Activity Register (PAR), and the outputs of the flip-flops are fed into a Priority Encoder circuit (PE) which generates the address of a switch adapter with which a connection can be established. In this manner, a high speed dynamic allocator of variable length time slots which solves controller bottleneck problems in time critical systems is realized.

REFERENCES:
patent: 4331956 (1982-05-01), Anderson
patent: 4630045 (1986-12-01), Georgion
patent: 4639910 (1987-01-01), Toegel et al.
patent: 4698801 (1987-10-01), Hatano et al.
patent: 4814762 (1989-03-01), Franaszek
patent: 4845704 (1989-07-01), Georgiou et al.

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