High-speed duty cycle control circuit

Details High-speed duty cycle control circuit High-speed duty cycle control circuit

2003-06-23

2004-11-16

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000

Reexamination Certificate

active

06819155

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to automatic test equipment, and more particularly circuits for controlling the duty cycle of high-speed differential clock signals.
BACKGROUND OF THE INVENTION
Many digital electronic systems require a periodic clock signal to synchronize the operations of various system sub-circuits. Most systems perform optimally when the clock duty cycle (the ratio of pulse width to total cycle time) is 50%, or 50/50. A 50% duty cycle is especially important for high speed semiconductor testing applications, such as timing generation circuitry, due to the desirability of a balanced jitter-free output.
FIG. 1A
illustrates a single-ended clock signal having an ideal 50% duty cycle. For each period, half the waveform is above a DC bias point, at 10 (in phantom), and half the waveform is below. A degraded clock signal exhibiting a 60/40 duty cycle is also shown in FIG.
1
A.
Unfortunately, establishing and maintaining a 50% duty cycle at high frequencies has proven problematic. This is especially true for systems that employ differential clock circuitry. A differential clock signal has two complementary signal components, either one of which may affect the resulting duty cycle if degraded or delayed with respect to one another in any way.
FIG. 1B
exhibits a differential clock signal corresponding to the 60/40 waveform of FIG.
1
A.
In the field of automatic test equipment, one alleged solution to controlling the duty cycle for a high-speed clock is proposed by DiTommaso, in U.S. Pat. No. 6,366,115. This proposal describes employing a buffer circuit having rising and falling edge delay circuits along with a signal path error correction circuit and a temperature-related error correction circuit to correct for duty cycle errors.
In operation, the rising and falling delay circuits receive error correction signals from the signal path error correction circuit and the temperature related error correction circuit. By shifting both the rising and falling edge delays according to a feedback loop that provides a signal indicative of the actual duty cycle, the output waveform may be modified to reflect a 50% duty cycle.
While the DiTommaso proposal appears beneficial for its intended applications, the amount of circuitry employed to achieve a closed-loop system, to delay both the rising and falling edges, and correct for signal path errors and temperature related errors may be undesirable for at-speed high performance testing. This may be especially true for timing-related circuitry operating at frequencies in excess of 2 gigahertz.
What is needed and as yet unavailable is a duty cycle correction circuit for differential clock signals that provides accurate duty cycle control with minimal additional circuitry and complexity. The duty cycle control circuit of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The high-speed duty cycle control circuit of the present invention provides high accuracy control for establishing a desired duty cycle for high speed differential signals. Moreover, the control circuit accomplishes this with minimal additional circuitry and low complexity.
To realize the foregoing advantages, the invention in one form comprises a duty cycle correction circuit for changing the duty cycle for a differential periodic signal. The duty cycle correction circuit includes input circuitry for receiving a first differential signal. The differential signal exhibits a first signal component and a complement signal component, each of the components having initial high and low signal levels and respective first and second DC bias levels. The input circuitry includes a differential output having a first path for propagating the first signal component and a second path for propagating the complement signal component. Programmable load circuitry couples to the differential output and includes a programmable input. The load circuitry operates to programmably vary the DC bias level of at least one of the signal components. A differential gain amplifier constructed similar to the input circuitry is coupled to the first differential output and disposed downstream of the load circuitry.
In another form, the invention comprises a method of changing the duty cycle of a differential signal having a first signal component and a complement signal component. Each of the signal components have initial high and low signal levels and respective DC bias levels. The method includes the steps: modifying the DC bias level of one of the signal components to a desired level, the modified signal component cooperating with the other signal component to form a modified differential signal; and restoring the initial high and low signal levels.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 6208199 (2001-03-01), Andersson
patent: 6366115 (2002-04-01), DiTommaso
patent: 6441663 (2002-08-01), Chuang et al.
patent: 6469493 (2002-10-01), Muething, Jr. et al.
patent: 6476645 (2002-11-01), Barnes
patent: 6501313 (2002-12-01), Boerstler et al.
patent: 6535015 (2003-03-01), Krishnan et al.
patent: 6566925 (2003-05-01), Ma
patent: 6593789 (2003-07-01), Atallah et al.
patent: 6600338 (2003-07-01), Nguyen et al.
patent: 6643790 (2003-11-01), Yu et al.
Published U.S. patent application No. 2002/0079939 to Nair et al.
Published U.S. patent application No. 2003/0016065 to Harrison et al.

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