Boots – shoes – and leggings
Patent
1987-03-11
1989-07-04
Harkcom, Gary V.
Boots, shoes, and leggings
364521, 364900, 340798, G06F 1562
Patent
active
048456403
ABSTRACT:
A high-speed graphics memory providing line mode and area mode data transfer at high speeds comprises a frame buffer structure, with unique address alignment and corresponding data manipulation to provide line mode and area mode pixel data transfer of comparable time intervals. The frame buffer comprises independently addressable 16 byte-wide video memories. The 16 memories provide a 128-bit contiguous horizontal pixel sequence in the line mode, and provide a two-dimensionally contiguous array of pixels comprising 8 bits by 2 bytes when in the area mode, from which an 8.times.8 bit area is selected at any address location in the entire image bit map. The pixels included in a particular line mode or area mode data transfer are directly addressable by external equipment, such as graphics processors, to provide a high-speed graphic display system.
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Sproull, R. F., Sutherland, I. E., Thompson, A., Gupta, S., Minter, C.; The 8.times.8 Display, Carnegie-Mellon University, Pittsburgh, Pa., Dec. 81.
BITBLT Processor, Electronic News, p. 38, 1/26/87.
Ballard Robert S.
Clark Steven D.
Harkcom Gary V.
Lacasse Randy W.
MegaScan Technology, Inc.
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