High speed DRAM architecture with uniform access latency

Details High speed DRAM architecture with uniform access latency High speed DRAM architecture with uniform access latency

2006-03-14

2006-03-14

Mai, Son (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S022000, C365S233100, C365S230030

Reexamination Certificate

active

07012850

ABSTRACT:
A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

REFERENCES:
patent: 4796234 (1989-01-01), Itoh et al.
patent: 5371714 (1994-12-01), Matsuda et al.
patent: 6850449 (2005-02-01), Takahashi

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