High speed double error correction plus triple error detection s

Details High speed double error correction plus triple error detection s High speed double error correction plus triple error detection s

1977-03-04

1978-09-26

Atkinson, Charles E.

Communications: electrical

Digital comparator systems

G06F 1112

Patent

active

041174585

ABSTRACT:
A single and double error correction and triple detection system using cyclical redundancy codes based on the generator polynomials:

REFERENCES:
patent: 3714629 (1973-01-01), Hong et al.
patent: 3814921 (1974-06-01), Nibby et al.
patent: 3851306 (1974-11-01), Patel
patent: 3859630 (1975-01-01), Bennett
patent: 3896416 (1975-07-01), Barrett et al.
patent: 4030067 (1977-06-01), Howell et al.
R. T. Chien, Memory Error Control; Beyond Parity, IEEE Spectrum, Jul. 1973, pp. 18-23.
V. K. Malhotra et al., A Double Error-Correction Scheme for Peripheral Systems, IEEE Trans. on Computers, vol. C-25, No. 2, Feb. 1976, pp. 105-114.

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