High-speed domino logic circuit

Details High-speed domino logic circuit High-speed domino logic circuit

2003-01-30

2004-03-30

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000, C327S212000, C326S098000, C326S121000, C326S122000

Reexamination Certificate

active

06714059

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to domino logic circuits.
BACKGROUND OF THE INVENTION
FIG. 1
shows a schematic diagram of one embodiment of a typical prior art domino logic circuit
100
. As seen in
FIG. 1
, prior art domino logic circuit
100
included a first supply voltage
101
, typically Vdd, coupled to a source, or first flow electrode
111
, of a PFET
110
and a source, or first flow electrode
121
of a PFET
120
, also known as a keeper transistor. The signal CLK was coupled to a control electrode or gate
115
of PFET
110
and a control electrode or gate
135
of an NFET
130
. A drain, or second flow electrode
113
, of PFET
110
was coupled to a first node
190
. A drain, or second flow electrode
123
, of PFET
120
was also coupled to first node
190
and an input terminal
107
of an inverter
105
. An output terminal
109
of inverter
105
was coupled to a control electrode or gate
125
of PFET
120
and a prior art domino logic circuit out terminal
151
.
Node
190
was coupled to an input terminal
102
of a logic block
103
. Logic block
103
was comprised of any one of numerous types of logic and/or circuitry used in the art including various logic gates, logic devices and circuits such as transistors, inverters and other logic functions, both simple and complex, well known to those of skill in the art, and too numerous to list comprehensively herein. Logic block
103
also included inputs at input terminals
104
and an output terminal
108
. Output terminal
108
of logic block
103
was coupled to a drain, or first flow electrode
131
of NFET
130
. A source, or second flow electrode of NFET
133
was coupled to a second supply voltage
106
, typically ground.
For illustrative purposes specific embodiments of prior art domino logic circuit
100
were shown with specific transistors. However, the NFETs and PFETS shown in the
FIG. 1
can be readily exchanged for PFETs and NFETs by reversing the polarities of the supply voltages or by other well known circuit modifications.
Prior art domino logic circuit
100
had two modes, or phases, of operation; a pre-charge phase and an evaluation phase. In one embodiment of prior art domino logic circuit
100
, in the pre-charge phase; the signal CLK was low or a digital “0”. Consequently, PFET
110
was conducting or “on”; PFET
120
was on and NFET
130
was off, thereby isolating logic block
103
from second supply voltage
106
. In addition, during the pre-charge phase, first node
190
was high, or a digital “1”, and this state was reinforced by PFET
120
being in the on state. In addition, during the pre-charge phase, prior art domino logic circuit output terminal
151
was low or digital “0”.
In the following discussion, assume that in the previous cycle, there was a path
191
from node
190
to second supply voltage
106
through logic block
103
. In the evaluation phase, the signal CLK was high or a digital “1”. Consequently, PFET
110
was not conducting or “off”; PFET
120
was on; and NFET
130
was on, thereby providing logic block
103
a path to second supply voltage
106
. In addition, during the evaluation phase, first node
190
was low, or a digital “0” and prior art domino logic circuit output terminal
151
was high or digital “1”.
Prior art domino logic circuit
100
functioned reasonably well in either low speed environments or low noise environments, however, prior art domino logic circuit
100
did not perform well in high speed and high noise applications. This was because, with prior art domino logic circuit
100
, the transition from the pre-charge phase to the evaluation phase involved an inherent problem regarding first node
190
and PFET
120
. This problem arose because, as discussed above, in the pre-charge phase, first node
190
of prior art domino logic circuit
100
was held at a digital “1” and prior art domino logic circuit output node
151
was a digital “0”, which reinforced the digital “1” on first node
190
by keeping PFET
120
on. At the transition from pre-charge to evaluation phase, the signal CLK goes to a digital “1” and NFET
130
is turned on, consequently, logic block
103
is provided with a path to second source voltage
106
. If, as was often the case in many instances and types of logic used in logic block
103
, logic block
103
also provided a path to NFET
130
at this time, i.e., logic block
103
was also “on”, then a path
191
from first node
190
(
FIG. 1
) to second supply voltage
106
, typically ground, through logic block
103
and NFET
130
was established. Once path
191
was established, first node
190
should have dropped to a digital “0” as rapidly as possible to avoid delays in operation of prior art domino logic circuit
100
. However, in this same time frame, PFET
120
was still transitioning to the off state, i.e., was still on, and this meant that PFET
120
was still trying to hold first node
190
at first supply voltage
101
, i.e., at a digital “1”. Consequently, in prior art domino logic circuit
100
there was an inherent “fight” between first node
190
, trying to discharge to “0” and PFET
120
trying to hold first node
190
at “1” during the transition between pre-charge and evaluation. This fight resulted in a significant delay in the operation of prior art domino logic circuit
100
.
To try and minimize this effect, i.e., the delay, resulting from the “fight” between first node
190
, trying to discharge to “0” and PFET
120
trying to hold first node
190
at “1” during the transition between pre-charge and evaluation, most circuit designers employed a PFET
120
with the smallest possible channel dimensions, i.e., PFET
120
was intentionally made small, and therefore weak, so that PFET
120
would hold node
190
high for as short a time as possible. In other words, PFET
120
was made weak and small so it would lose its fight with first node
190
quickly. Unfortunately, this solution had significant drawbacks. In particular, by making PFET
120
small, the noise immunity of prior art domino logic circuit
100
was compromised and this could lead to total failure of prior art domino logic circuit
100
in high noise environments.
Employing a weak PFET
120
in prior art domino logic circuit
100
was particularly problematic in instances where logic block
103
did not provide a path to NFET
130
and second supply voltage
106
. In these instances, first node
190
must remain high. However, if noise was introduced at input terminals
104
of logic block
103
, this noise could cause logic block
103
to provide a temporary path to NFET
130
and second supply voltage
106
. In this case, first node
190
could discharge to ground, i.e., first node
190
could go low in error, and there was no mechanism to ever bring first node
190
back to high or digital “1”. Consequently, under these circumstances, prior art domino logic circuit
100
would fail unrecoverably.
As a result of the situation discussed above, designers of prior art domino logic circuit
100
were constantly involved in a balancing act between minimizing the size and strength of PFET
120
, to increase speed of prior art domino logic circuit
100
, and increasing the size and strength of PFET
120
, to make prior art domino logic circuit
100
more robust and noise immune. The result was that prior art domino logic circuit
100
functioned reasonably well in either low speed environments or low noise environments, however, prior art domino logic circuit
100
did not perform well in high speed and high noise applications.
What is needed is a method and apparatus for creating an improved domino logic circuit that is capable of operation in both high speed and high noise environments.
SUMMARY OF THE INVENTION
The present invention is directed to a method and apparatus for creating an improved domino logic circuit that is capable of operation in both high speed and high noise environments.
The improved high-speed domino logic circuit of the invention uses two delayed c

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