High speed dominant mode bus for differential signals

Details High speed dominant mode bus for differential signals High speed dominant mode bus for differential signals

1993-06-21

1996-02-20

Harvey, Jack B.

Multiplex communications

Wide area network

Packet switching

370 859, 370123, H04J 302

Patent

active

054936578

ABSTRACT:
A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission. A biasing circuit for the bus drivers allows operation at low voltages, and furthermore insures that the zero crossing of crossing of the differential voltage signal on the second differential bus.

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