High speed divider with square root capability

Details High speed divider with square root capability High speed divider with square root capability

1990-04-02

1992-07-07

Mai, Tan V.

Boots, shoes, and leggings

364752, G06F 752

Patent

active

051288915

ABSTRACT:
An apparatus for performing the division of a first operand by a second operand by iteratively producing a series of partial remainders and predicted quotient bits utilizing the generation of multiples of the second operand and the selection of one of the generated multiples. The second operand is first selected as a first partial remainder. A first quotient bit is predicted from the first and second operands and a next quotient bit is predicted from the partial remainder and the second operand. One of the generated multiples is selected for producing a next partial remainder based upon the next quotient prediction. A next partial remainder is then produced from the produced partial remainder and the selected multiple of the second operand.

REFERENCES:
patent: 4075704 (1978-02-01), O'Leary
patent: 4546447 (1985-10-01), Sawada
patent: 4683547 (1987-07-01), DeGroot
patent: 4688186 (1987-08-01), Ferrell et al.
patent: 4722069 (1988-01-01), Ikeda
patent: 4724529 (1988-02-01), Irukulla
patent: 4878190 (1989-10-01), Darley et al.
patent: 4939686 (1990-07-01), Fandrianto
patent: 4979142 (1990-12-01), Allen et al.
Birman et al., "Developing the WTL3170/3171 Sparc Floating-Point Coprocessors", IEEE Micro, pp. 55-64, Feb. 1990.

Affiliated with

Also associated with

Rating

High speed divider with square root capability does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed divider with square root capability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed divider with square root capability will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1834643