High speed divider for phase-locked loops

Details High speed divider for phase-locked loops High speed divider for phase-locked loops

1995-12-20

1997-03-25

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 377 44, 377 48, 377 52, H03K 2138, H03L 7193

Patent

active

056148690

ABSTRACT:
A high speed divider circuit is provided for phase-locked loops (PLLs). The divider circuit in the feedback loop of the PLL has two divider circuits, a prescalar divide-by-4 circuit, which receives the high frequency signal from the voltage-controlled oscillator (VCO) of the PLL, and a programmable divide-by-N circuit, which resets itself after counting up to N. Responsive to the reset signal from the divide-by-N circuit, the prescalar divider circuit divides the VCO signal by 4+P, where P is a programmable value. This programmable periodic change in the divisor of the prescalar divide circuit allows the divisor in the classic PLL frequency synthesis equation to be set to nearly any number so that the synthesized output frequency of the PLL can be set with very fine resolution.

REFERENCES:
patent: 4179670 (1979-12-01), Kingsbury
patent: 4633194 (1986-12-01), Kikuchi et al.

Affiliated with

Also associated with

Rating

High speed divider for phase-locked loops does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed divider for phase-locked loops, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed divider for phase-locked loops will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2206811