High speed divide by 1.5 clock generator

Details High speed divide by 1.5 clock generator High speed divide by 1.5 clock generator

1995-04-25

1996-09-03

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327159, 327218, 327225, 377 48, H03B 1900

Patent

active

055527329

ABSTRACT:
A simple, reliable, divide by 1.5 clock generator is provided. This is done by using a divide by 3 circuit with three gates. The first two gates are clocked by the RLL clock, and the third gate is clocked by the inverse of the RLL clock. The output of the first gate is combined with the RLL clock to provide an output pulse. Another output is produced when the output of the third gate is combined with the inverse of the RLL clock. The combination of these two outputs thus produces a divide by 1.5 clock with a precisely placed rising edge. The output clock is not symmetrical, but the rising edge (or the falling edge on its inverse) is precisely placed at the 1.5 frequency.

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patent: 5390223 (1995-02-01), Lindholm
patent: 5475322 (1995-12-01), MacDonald

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