High speed digitally voltage controlled oscillator

Details High speed digitally voltage controlled oscillator High speed digitally voltage controlled oscillator

2002-03-14

2004-01-27

Lam, Tuan T. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C327S107000, C327S299000

Reexamination Certificate

active

06683501

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application Ser. No. 91100919, filed Jan. 22, 2002.
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates in general to a digitally voltage controlled oscillator. More particularly, the invention relates to a high-speed digitally voltage controlled oscillator that can avoid excessive phase error caused by process parameter variation, and is applicable to high resolution and high frequency operation.
2. Description of the Related Art
To realize high-speed digital phase locked loop (DPLL), a voltage controlled oscillator (VCO) with a resolution of 1/N phase is typically employed. The operation theory of a high-speed digital phase locked loop includes comparing a frequency of a standard clock signal generated by a crystal oscillator with a frequency of an output clock signal of the high-speed digitally voltage control oscillator via a phase detector. When the frequency of the standard clock signal is larger than the frequency of the output clock signal, the phase detector informs the high-speed digitally voltage controlled oscillator to increase the frequency of the output clock signal. When the frequency of the standard clock signal is smaller than the frequency of the output clock signal, the phase detector informs the high-speed digitally voltage controlled oscillator to decrease the frequency of the output clock signal. When the frequency of the standard clock signal and is the same as the frequency of the output clock signal, the digital phase locked loop is locked, and the current output clock is output.
There are two conventional methods to realize a high-speed digitally voltage controlled oscillator with a resolution of 1/N phase. One method is to use a delay-line, the other is to use a counter with an input frequency N times of an output frequency thereof. Assuming that N=24, the high-speed digitally voltage controlled oscillator requires 24 orders of delay lines to obtain the resolution of 1/24 phase. This many delay lines results in an excessive phase error caused by process parameter variation. As N increases, the situation is worsened. The other method using a counter with an input frequency 24 times an output frequency thereof to obtain the high-speed digitally voltage controlled oscillator with a resolution of 1/24 phase is complex and difficult to fabricate. Such a method is thus only suitable for low resolution and low frequency application.
Accordingly, prior art has the following disadvantages: limited by process parameter variation; and suitable for low resolution and low frequency application only.
SUMMARY OF INVENTION
The invention provides a high-speed digitally voltage controlled oscillator. By reducing the number of delay lines and frequency multiple of the counter, the excessive phase error caused by process parameter variation is avoided, and the high-speed digitally voltage controlled oscillator is applicable for high resolution and high frequency operation.
The high-speed digitally voltage controlled oscillator provided by the invention comprises a load counter, a 1/N phase difference generator (N is an integer larger than 1), a multiplexor, a clock selector and a load controller. The load counter receives a load count and a reference clock signal. After counting zero, the load counter counts a new load count value and continues counting, and outputs the count value. The load count value includes D−1 (D is an integer larger 1), D and D+1. The 1/N phase difference generator is coupled to the load counter to receive the load count value and the reference clock signal, so as to generate M (M is an integer larger than 1). Every two neighboring clock signals have a 1/N phase difference therebetween, and N=M×(D+1). The multiplexor is coupled to the 1/N phase difference generator to receive the clock signals and a clock select signal, so as to select one of the clock signals as an output clock signal. The clock selector is coupled to the multiplexor to receive either a digit carry signal or a digit borrow signal, the count value, and the reference clock signal, and to generate the clock select signal according to either one of the digit carry and regress signals, and the count value. The load controller is coupled to the clock selector and the load controller to receive either the digit carry or regress signal, the clock select signal, the count value and the reference signal, and to output the load count value according thereto.
In one embodiment of the invention, the 1/N phase difference generator comprises a first clock generator, a first set of phase adjusters, a second clock generator and a second set of phase adjusters. The first clock generator is coupled to the load counter to receive the count value and the reference clock signal, and to sample the count value to generate a first clock signal among the clock signals at a positive edge of the reference clock signal. The first set of phase adjusters comprises (M/2−1) phase adjusters coupled to the first clock generator to receive the first clock signal, and to perform phase adjustment, so as to output a second to a (M/2)th clock signals among the clock signals. Thereby, each of the second to the (M/2)th clock signals becomes the 1/N phase delay of the first to the (M/2−1)th clock signals sequentially. The second clock generator is coupled to the first clock generator to receive the first clock signal, and to sample the first clock signal, so as to generate a (M/2+1)th clock signal at the negative edge of the reference clock signal. The second set of phase adjusters comprises (M/2−1) phase adjusters coupled to the second phase generator to receive the (M/2+1)th clock signal, so as to perform phase adjustment and to output the (M/2+2)th to the Mth clock signals. Thereby, each of the (M/2+2)th to the Mth clock signals becomes the 1/N phase delay of each of the (M/2+1)th to the (M−1)th clock signals.
The frequency of the first clock signal is obtained by dividing the frequency of the reference clock signal by the sum of the count value and 1. The frequency of the (M/2+1)th clock signal is the frequency of the reference signal divided by the count value plus 1. The phase difference between the first clock signal and the (M/2+1)th clock signal is 180° with respect to the reference clock signal, while phase of the first clock signal is fixed at 0° with respect to the reference clock signal. The (M/2+1)th clock signal is fixed at 180° with respect to the reference clock signal. In addition, each of the first and second set of adjusters can be adjusted with an arbitrary phase.
In one embodiment of the invention, among any of the second to the Mth clock signals and when the digit carry signal is enabled, the clock signal prior to any of the second to the Mth clock signals is selected by the clock select signal. Among any of the first to the (M−1)th clock signals and when the digit borrow signal is enabled, the clock signal after any of the first to the (M−1)th clock signals is selected by the clock select signal. In the first clock signal and when the digit carry signal is enabled, the load controller loads D−1 into the load counter, and the clock select signal selects the Mth clock signal. In the Mth clock signal and when the digit borrow signal is enabled, the load controller loads D+1 into the load counter, and the clock select signal selects the first clock signal.
The frequency of the reference clock signal is the frequency of the output clock signal multiplied by D+1. The count value includes L digits (L is a positive integer). The load counter includes a down counter.
In the above embodiment, the digit carry and regress signals are generated by a phase detector. When the digit carry signal is enabled, it indicates that the output clock signal has to advance 1/N phase with respect the output clock signal. When the digit borrow signal is enabled, the output clo

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