High speed digital to analog converter

Details High speed digital to analog converter High speed digital to analog converter

2003-06-10

2004-08-24

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S137000

Reexamination Certificate

active

06781537

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This is the first application filed for the present invention.
MICROFICHE APPENDIX
Not Applicable
TECHNICAL FIELD
The present invention relates in general to signal processing, and in particular to a high speed digital to analog converter.
BACKGROUND OF THE INVENTION
Digital to Analog (D/A) converters are very well known in the art. In general, D/A converters are designed to convert an N-bit digital value into a corresponding analog signal level. The number (N) of bits forming the N-bit digital value may be as low as two, but 6- and 8-bit D/A converters are ubiquitous, and 16-bit D/A converters are not uncommon.
As shown in
FIG. 1
, a typical D/A converter
2
utilizes a ladder (or inverted ladder) structure
4
driven by a precision voltage reference (Vref) to equalize logic levels across each of the bits (B
1
-B
6
)of an input digital word
6
. The equalized bits are then added, (using, for example, a conventional Operational Amplifier [Op-Amp] based analog voltage ADDer
8
to generate the desired level of the output analog signal
10
. As may be seen in
FIG. 1
, precise selection of input resistor values (R
1
-R
6
) provides input scaling, so that each bit (B
i
) makes an appropriate (additive) contribution (S
i
) to the total value (S) of the analog output
10
. Thus, for example, the total output signal level (S) will be given by
S
=
∑
i
=
1
N
⁢
 
⁢
S
i
,
and the resistor values will be selected such that the response to each of the input data bits (B
1
-B
6
) follows the conventional binary powers of two; that is, for the ith input data bit (B
i
), the response, in terms of the contribution (S
i
) to the total output signal level (S) will be proportional to S
i
=2
i−1
·B
i
.
Other D/A converter designs are known. A limitation of all conventional D/A converters is that propagation delays within the converter impose severe speed limitations. At data rates below a few MHz, these speed limitations do not produce severe problems. However, as data rates increase beyond a few 10's of MHz, propagation delays become increasingly problematic. In addition, as data rates increase into the radio frequency (rf) and microwave range, gain/bandwidth limitations and signal reflections due to impedance mismatches become progressively significant. All of these effects render accurate high speed D/A conversion very difficult.
U.S. Pat. No. 5,408,498, which issued to Yoshida on Apr. 18, 1995 teaches a serial signal transmission system in which a binary serial data signal is converted into a quaternary serial signal for transmission. Thus the binary serial data signal is treated as a string of successive 2-bit digital values, which are converted into corresponding 4-level analog symbols for transmission. At the receiver, incoming 4-level analog symbols are decoded (e.g. by comparing each symbol to a set of predetermined threshold levels) to recover the original 2-bit digital values and thereby restore the binary serial data signal. Thus the system of Yoshida provides a 2-bit D/A converter capable of producing a 4-level analog output signal. This system has the benefit of reducing the symbol rate through the transmission system (by a factor of two) without loss of data.
The use of a 4-level analog signal for transmission means that the threshold levels used for decoding the symbols can be separated comparatively widely. This provides some noise tolerance, and also relaxes the requirement for accurate D/A conversion in the transmitter. This, in turn, allows the D/A converter to be run at higher speeds, because some degradation in the accuracy of D/A conversion is permissible.
However, in some applications, it is desirable to provide accurate digital-to-analog conversion of multi-bit digital values, and at very high data rates. For example, Applicant's co-pending U.S. patent application Ser. No. 10/262,944, entitled Electrical Domain Compensation Of Optical Dispersion In An Optical Communications System, filed on Oct. 3, 2002, teaches a system for compensating chromatic dispersion in an optical communications system, by predistorting an input binary signal, and then using the predistorted signal to drive optical modulators. In this application, D/A conversion to at least 5 bits precision, at a sample rate that is double the bit rate is necessary for successful compensation of dispersion. At sufficiently low bit-rates, known D/A converters can be employed to provide the necessary functionality. However, it is desirable to provide bit rates of 10.7 GB/s, which implies a requirement for a D/A converter running at a sample rate of 21.4 Gigasamples-per-second. No known devices are capable of providing accurate D/A conversion at that speed.
Accordingly, a method and system for enabling high speed digital-to-analog conversion remains highly desirable. For the purposes of the present invention, “high speed digital-to-analog conversion” shall be understood to refer to digital-to-analog conversion in which N-bit digital values (where N≧4) are latched into the D/A converter, and corresponding 2
N
-level analog samples output from the D/A converter, at a sample rate of 2 Gigasamples-per-second or faster.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a high speed Digital to Analog (D/A) converter.
Thus, an aspect of the present invention provides a high speed Digital to Analog (D/A) converter. The D/A converter includes a phase aligner, and a vector summation block. The phase aligner operates to ensure precise phase alignment between corresponding bits of a parallel N-bit digital signal having a data rate of at least 2 GHz. The vector addition block performs a vector addition of the phase-aligned bits of the parallel N-bit digital signal.
In embodiments of the invention, the vector addition block includes means for weighting each bit of the parallel N-bit digital signal, and a microwave signal combiner network for adding the weighted bits of the parallel N-bit digital signal. The microwave signal combiner network can be provided as either a multistage parallel cascade of impedance matched junctions, or a linear cascade of junctions. The weighting means may be provided by an attenuator array and/or an insertion loss of each junction forming the combiner network.


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