High-speed digital timing and gain gradient circuit...

Details High-speed digital timing and gain gradient circuit... High-speed digital timing and gain gradient circuit...

1999-02-24

2003-10-21

Tran, Khai (Department: 2631)

Pulse or digital communications

Synchronizers

C341S139000, C708S319000

Reexamination Certificate

active

06636572

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a system and a method for increasing throughput rate of a signal processor. In particular, it provides a system and method for parallel processing of a digital feedback signal using a high-speed gradient circuit such as a timing or gain gradient circuit, or both.
BACKGROUND
A “digital signal” is a signal that conveys a discrete number of values at discrete times. Contrast the “analog signal,” i.e., a signal that conveys an infinite number of values on a time continuum. A signal having a digital form may be generated from an analog signal through sampling and quantizing the analog signal. Sampling an analog signal refers to “chopping” the signal into discrete time periods and capturing an amplitude value from the signal in selected ones of those periods. The captured value becomes the value of the digital signal during that sample period. Such a captured value is referred to as a sample.
Quantizing refers to approximating a sample with a value that may be represented on a like digital signal. For example, a sample may lie between two values characterized upon the digital signal. The value nearest (in absolute value) to the sample may be used to represent the sample. Alternatively, the sample may be represented by the lower of the two values between which the sample lies. After quantization, a sample from an analog signal may be conveyed as a digital signal. This is the resultant signal upon which the digital circuit may operate.
A digital signal processor (DSP) transforms an input digital signal to an output digital signal. For the digital filter, the transformation involves filtering out undesired portions of the received digital signal. An original analog signal may be represented as a sum of a plurality of sinusoids. Each sinusoid oscillates at a particular and unique frequency. Filtering is used to remove certain frequencies from an input signal while leaving other frequencies intact.
Programs executing on digital circuits often do so in “real-time.” Real-time programs are programs that must execute within a certain time interval. Regardless of whether a program executes in a large period of time or a small period of time, the result of executing the program is the same. However, if real-time programs attempt to execute in an amount of time longer than the required time interval, then they no longer will compute the desired result.
Programs executing on a digital circuit are real-time programs in that the instructions are manipulating a sample of a digital signal during the interval preceding the receipt of the next sample. If the program cannot complete manipulating a sample before the next sample is provided, then the program will eventually begin to “lose” samples. A lost sample does not get processed, and therefore the output signal of the digital circuit no longer contains all of the information from the input signal provided to the digital circuit. This potential for losing samples is reduced by a preferred embodiment of the present invention, while maintaining a required throughput rate.
A digital circuit may be programmed to modify signals. The number of instructions required to do this is relatively fixed. A digital circuit must be capable of executing this relatively fixed number of instructions on any given sample before the next sample of the series is provided.
Besides considering a digital circuit's throughput, all design parameters have an associated cost. One important cost factor is the silicon area needed to “house” the digital circuit. Those that are manufactured on a relatively small silicon chip are less expensive than those requiring a large chip. Therefore, an easily manufacturable, small (low cost) digital circuit is desirable.
Some features of digital circuits that are important to the design engineer include phase characteristics, stability, and coefficient quantization effects. To be addressed by the designer are concerns dealing with finite word length and circuit performance. order than a generic Nyquist filter to implement the required shape factor. DIGITAL FIR filters are subject to non-negligible inter-symbol interference (ISI), however.
Coefficient quantization error occurs as a result of the need to approximate the ideal coefficient for the “finite precision” processors used in real systems. Quantization error sources due to finite word length include:
a) input/output (I/O) quantization,
b) filter coefficient quantization,
c) uncorrelated roundoff (truncation) noise,
d) correlated roundoff (truncation) noise, and
e) dynamic range constraints.
Input noise associated with the analog-to-digital (A/D) conversion of continuous time input signals to discrete digital form and output noise associated with digital-to-analog conversion are inevitable in digital filters. Uncontrolled propagation of this noise is not inevitable, however.
Uncorrelated roundoff errors most often occur as a result of multiplication errors. For example, in attempting to maintain accuracy for signals that are multiplied, only a finite length can be stored and the remainder is truncated, resulting in “multiplication” noise being propagated. Obviously, any method that minimizes the number of multiplication steps will also reduce noise and increase inherent accuracy.
Correlated roundoff noise occurs when the products formed within a digital filter are truncated. These include the class of “overflow oscillations.” Overflows are caused by additions resulting in large amplitude oscillations. Correlated roundoff also causes “limit-cycle effect” or small-amplitude oscillations. For systems with adequate coefficient word length and dynamic range, this latter problem is negligible. However, both overflow and limit-cycle effects force the digital filter into non-linear operation. Both of these latter constraints are addressed by a preferred embodiment of the present invention.
Constraints to dynamic range, such as scaling parameters, are used to prevent overflows and underflows of finite word length registers. For a digital circuit, an overflow of the output produces an error. If the input has a maximum amplitude of unity, then worst case output is:
y
⁡
(
n
)
=
∑
n
-
0
N
-
1
⁢
 
⁢
x
⁡
(
n
)
=
s
(
1
)
where:
s=scaling factor
x(n)=input sample value at n
y(n)=output sample value at n
Guaranteeing y(n) is a fraction means that either the circuit's gain or the input has to be scaled down by “s.” Reducing gain implies scaling the digital filter's coefficients, for example, to the point where a 16-bit coefficient, for example, would no longer be used efficiently. Another result of this scaling is to degrade frequency response due to high quantization errors. A better alternative is to scale the input signal. Although this results in a reduction in signal-to-noise ratio (SNR), the scaling factor used is normally <2, not altering the SNR drastically. Systems employing circuits requiring use of reduced bandwidth are less susceptible to degradation of the SNR. This is also addressed by a preferred embodiment of the present invention.
A typical example of a high-speed digital circuit is a digital FIR filter with five or more coefficients known as a Type II FIR. A Type II FIR filter is based on an array of costly Multiply and Add (MAC) accumulation stages. A conventional system using MAC is constrained to a minimum number of gates to achieve a given partial product accuracy. Digital implementation of an FIR filter is also limited by the maximum number of logic gates that can be inserted between reclocking stages established by the filter's clock cycle. Thus, for a given digital process, a minimum time to process is established by the propagation time through the critical path. To achieve very high speeds of processing, the critical path is broken into a number of shorter paths that can be addressed at higher clock speeds, i.e., processed within a short clock cycle. A preferred embodiment of the present invention implements an alternative using parallel processing including pa

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